Hysteresis timing scheme for mode transition in a buck boost converter
US10594218B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Dec 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1588
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A buck boost converter includes a buck boost converter circuit to generate an output voltage in response to an input voltage, and a mode control logic circuit to generate a mode control signal to control an operation mode of the buck boost converter circuit to operate in one of a buck mode, a boost mode, and a buck-boost mode. The buck boost converter circuit includes an upper buck transistor coupled to an input voltage node, the input voltage node to receive the input voltage, an upper boost transistor coupled to an output voltage node, the output voltage node to output the output voltage, and an inductor coupled between the upper buck transistor and the upper boost transistor. The mode control signal is generated based on a first duty cycle of the upper buck transistor and a second duty cycle of the upper boost transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.