Apparatus comprising a phase-locked loop
US10594327B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Aug 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/191
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.