Data transfer between asynchronous clock domains
US10599178B2 · kind B2 · utility
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12References
17Claims
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Key dates
| Filing date | Jul 16, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Jul 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.