Patent · US Active

Management of core power state transition in a microprocessor

US10599207B2 · kind B2 · utility

1Cited by

26References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Malcolm S. Allen-Ware · Tucson, US
Charles R. Lefurgy · Austin, US
Karthick Rajamani · Austin, US
Todd J. Rosedahl · Zumbrota, US
Guillermo J. Silva · Austin, US
Gregory S. Still · Raleigh, US
Victor Zyuban · Yorktown Heights, US

Key dates

Filing date	Dec 7, 2017
Grant date	Mar 24, 2020
Priority date	—
Expiry date	Dec 7, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.