Processor, computing device including the same and method of selecting low power mode of the same
US10599210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | May 31, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.