Systems and methods for enhanced ROM access resiliency
US10599523B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Feb 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/805
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system may include at least one processor, a management controller, a serial peripheral interface (SPI) read-only memory (ROM), and at least one logic device. The management controller may be communicatively coupled to the at least one processor and configured to provide out-of-band management of the information handling system. The logic device may be configured to reset the SPI ROM in response to an indication that the SPI ROM is to be reset, and the resetting may include detaching the SPI ROM from a SPI controller, disconnecting a power source from the SPI ROM, in response to a passage of a particular amount of time, reconnecting the power source to the SPI ROM, and re-attaching the SPI ROM to the SPI controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.