Efficient breakpoint detection via caches
US10599541B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2019 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Mar 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficient breakpoint detections via caches comprises monitoring a memory location by detecting cache misses on a cache. Embodiments include identifying a memory address that is to be monitored, storing the memory address in a breakpoint monitoring list, and ensuring that any cache lines overlapping with the memory address are evicted from a cache. Based at least on an indication of an occurrence of a cache miss, embodiments determine whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list. When the portion of the imported cache line does overlap with the memory address, embodiments process one or more monitoring operations on the memory address, and, based on the memory address being stored in the breakpoint monitoring list, embodiments evict the imported cache line from the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.