Non-coherent read in a strongly consistent cache system for frequently read but rarely updated data
US10599567B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Oct 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique relates to enabling a multiprocessor computer system to make a non-coherent request for a cache line. A first processor core sends a non-coherent fetch to a cache. In response to a second processor core having exclusive ownership of the cache line in the cache, the first processor core receives a stale copy of the cache line in the cache based on the non-coherent fetch. The non-coherent fetch is configured to obtain the stale copy for a predefined use. Cache coherency is maintained for the cache, such that the second processor core continues to have exclusive ownership of the cache line while the first processor core receives the stale copy of the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.