Double glitch capture mode power integrity analysis
US10599798B1 · kind B1 · utility
2Cited by
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20Claims
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Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Mar 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data is received that characterizes an integrated circuit and which includes a plurality of Standard Test Interface Language (STIL) codes and at least one file defining physical and/or logical parameters of the integrated circuit. Thereafter, using the received data, a power integrity analysis of the integrated circuit is performed to estimate power induced noise in a double glitch capture mode. Data is then provided that characterizes the performed double glitch capture mode power integrity analysis of the integrated circuit. Related apparatus, systems, techniques and articles are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.