Patent · US Active

Multi-tier co-placement for integrated circuitry

US10599806B2 · kind B2 · utility

3Cited by

3References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Xiaoqing Xu · Austin, US
Brian Tracy Cline · Austin, US
Stephen Lewis Moore · Austin, US
Saurabh Sinha · Danbury, US

Key dates

Filing date	Mar 28, 2018
Grant date	Mar 24, 2020
Priority date	—
Expiry date	Jun 21, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2111/20
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without the inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without the inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without the inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.