32-bit address space containment to secure processes from speculative rogue cache loads
US10599835B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 23, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Sep 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are disclosed to mitigate the meltdown vulnerability by selectively using page table isolation. Page table isolation is enabled for 64-bit applications, so that unprivileged areas in the kernel address space cannot be accessed in user mode due to speculative execution by the processor. On the other hand, page table isolation is disabled for 32-bit applications thereby providing mapping into unprivileged areas in the kernel address space. However, speculative execution is limited to a 32-bit address space in a 32-bit application, and s access to unprivileged areas in the kernel address space can be inhibited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.