Semiconductor device having a multi-terminal transistor layout
US10600351B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Aug 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a gate region, a source/drain region and an insulating layer between the gate region and the source/drain region. The source/drain region includes a first leg extending in a first direction, a second leg extending in parallel with the first leg, and a third leg connected between the first leg and the second leg.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.