Bitcell state retention
US10600462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Aug 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1695
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.