Vertical memory devices with common source including alternately repeated portions having different widths
US10600805B2 · kind B2 · utility
3Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Oct 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.