Comparator
US10601411B2 · kind B2 · utility
0Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Sep 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator includes a differential pair circuit comprising NMOS transistors, the differential pair circuit configured to output a signal corresponding to a difference between first and second input signals supplied thereto, and an input circuit configured to raise a voltage level of the first input signal supplied to the differential pair circuit when the voltage of the first input signal is less than a predetermined threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.