Receiver circuit with low power consumption and method for reducing power consumption of receiver system
US10601519B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Dec 1, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/69
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receiver circuit with low power consumption and a method for reducing power consumption of a receiver system are provided. The method for reducing power consumption of the receiver system comprises steps of: providing a signal receiver module; intermittently enabling/disabling the signal receiver module when a microprocessor is in a sleep mode; detecting whether the signal receiver module receives a signal when the signal receiver module is enabled; and waking the microprocessor up to decode the received signal if the signal receiver module receives the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.