Methods and apparatus for performing partial reconfiguration in a pipeline-based network topology
US10606779B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2016 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Nov 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output of the bus switch. The bus switched may be configured to route an incoming packet to a selected one of the two processing nodes in that pipeline stage or may only route the incoming packet to the active node if the other node is undergoing partial reconfiguration. Configured in this way, the hybrid topology supports partial reconfiguration of the processing nodes without disrupting or limiting the operating frequency of the overall network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.