Systems, methods, and apparatuses for implementing a thermal solution for 3D packaging

US10607909B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Purushotham Kaushik Muthur Srinath · Chandler, US
• Pramod Malatkar · Chandler, US
• Sairam Agraharam · Chandler, US
• Chandra Mohan Jha · Tempe, US
• Arnab Choudhury · Kirkland, US
• Nachiket R. Raravikar · Chandler, US

Key dates

• Filing date: Apr 2, 2016
• Grant date: Mar 31, 2020
• Expiry date: Apr 2, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/157
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.