On-chip network in programmable integrated circuit
US10608640B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2019 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | May 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and computer programs are presented for implementing a network on chip (NOC). One programmable integrated circuit comprises a plurality of clusters, an internal network on chip (iNOC), and an external network on chip (eNOC) outside the plurality of clusters. The plurality of clusters is disposed on a plurality of cluster rows and a plurality of cluster columns, each cluster comprising programmable logic. Further, the iNOC comprises iNOC rows and iNOC columns. Each iNOC row is configured for transporting data and comprising connections to clusters in a cluster row and the eNOC, and each iNOC column is configured for transporting data and comprising connections to clusters in a cluster column and the eNOC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.