Inter-stage gain calibration in double conversion analog-to-digital converter
US10608655B1 · kind B1 · utility
4Cited by
39References
26Claims
0Family size
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Key dates
| Filing date | Dec 6, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Dec 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various background calibration techniques to calibrate inter-stage gain, e.g., in pipelined ADCs, are described to allow open loop amplifier circuits to be used as residue amplifiers for better power efficiency. Using various techniques, a well-controlled perturbation can be injected between two conversions and the actual perturbation after a residue amplifier can be measured. By comparing the actual measurement against an expected value, the gain information of the residue amplifier can be estimated and then calibration can be applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.