Method and apparatus for error correction coding in communication
US10608665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Mar 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/255
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.