Device and method for calibrating a voltage regulator
US10613561B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Oct 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An integrated circuit includes a voltage monitor circuit having a first input coupled to a reference voltage and a second input, a successive approximation register (SAR) circuit having an input coupled to an output of the voltage monitor circuit, a low drop out (LDO) regulator having an input coupled to an output of the SAR circuit and an output coupled to the second input, a discharge circuit coupled to the LDO output, voltage sensing circuit having a first input coupled to the reference voltage during a trim mode and coupled to the LDO output during a monitor mode, having a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the first input goes higher or lower than the reference voltage by a predetermined amount. Control circuitry is configured to, during trim mode, periodically discharge the LDO output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.