Low power half-VDD generation circuit with high driving capability
US10613569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Apr 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45551
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.