Buffer management in a data storage device wherein a bit indicating whether data is in cache is reset after updating forward table with physical address of non-volatile memory and jettisoning the data from the cache
US10613985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2017 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Dec 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing data buffers in a data storage device. In some embodiments, a write manager circuit stores user data blocks in a write cache pending transfer to a non-volatile memory (NVM). The write manager circuit sets a write cache bit value in a forward map describing the NVM to a first value upon storage of the user data blocks in the write cache, and subsequently sets the write cache bit value to a second value upon transfer of the user data blocks to the NVM. A read manager circuit accesses the write cache bit value in response to a read command for the user data blocks. The read manager circuit searches the write cache for the user data blocks responsive to the first value, and retrieves the requested user data blocks from the NVM without searching the write cache responsive to the second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.