Device, system and method to access a shared memory with field-programmable gate array circuitry without first storing data to computer node

US10613999B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Francesc Guim Bernat · Barcelona, ES
• Thomas Willhalm · Sandhausen, DE
• Karthik Kumar · Chandler, US
• Daniel Rivas Barragan · Cologne, DE
• Patrick Lu · Chandler, US

Key dates

• Filing date: Jan 12, 2018
• Grant date: Apr 7, 2020
• Expiry date: Jun 15, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/24
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Techniques and mechanisms for providing a shared memory which spans an interconnect fabric coupled between compute nodes. In an embodiment, a field-programmable gate array (FPGA) of a first compute node requests access to a memory resource of another compute node, where the memory resource is registered as part of the shared memory. In a response to the request, the first FPGA receives data from a fabric interface which couples the first compute node to an interconnect fabric. Circuitry of the first FPGA performs an operation, based on the data, independent of any requirement that the data first be stored to a shared memory location which is at the first compute node. In another embodiment, the fabric interface includes a cache agent to provide cache data and to provide cache coherency with one or more other compute nodes.