Honoring pin insertion delay during clock tree synthesis
US10614261B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2019 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Feb 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure address systems and methods for dynamically adjusting skew windows during clock tree synthesis (CTS). A method may include identifying a pin insertion delay (PID) assigned to a clock sink in a set of clock sinks of a buffer tree in an integrated circuit design. The method further includes determining a skew window for the clock sink based on a skew target and adjusting the skew window based on identifying the PID assigned to the clock sink. The skew window is adjusted based on a skew adjustment parameter. The method further includes building a clock tree based on the buffer tree and the adjusted skew window. The building of the clock tree comprises tuning a clock path delay of the clock sink according to the adjusted skew window. A layout instance may be generated for the IC design based in part on the clock tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.