Device, method and system for on-chip generation of a reference clock signal
US10614774B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Jul 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.