Encapsulation process for semiconductor devices
US10615057B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Dec 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of encapsulating integrated circuits is disclosed. The method includes placing a front side of a semiconductor wafer, having partially cut scribe lines that separate a plurality of semiconductor dies, onto a backside of a dicing tape, grinding a backside of the cut semiconductor wafer to singulate the plurality of semiconductor dies, exposing the backside of the dicing tape to ultraviolet (UV) light to soften the dicing tape between each of the plurality of semiconductor dies and stretching the dicing tape to increase a distance between the plurality of semiconductor dies, laminating a backside and sides of each of the plurality of semiconductor dies with a first layer of encapsulant material, exposing a front side of the dicing tape to UV light to release the dicing tape from the plurality of semiconductor dies, and laminating a front side of the semiconductor dies with a second layer of encapsulant material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.