Decoupling capacitor circuit
US10615157B2 · kind B2 · utility
0Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Jun 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A decoupling capacitor includes a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library, a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library, a second PMOS transistor connected between the first NMOS transistor and the power rail, and a second NMOS transistor connected between the first PMOS transistor and the ground rail, wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.