Array substrate and manufacturing method thereof
US10615188B2 · kind B2 · utility
1Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2016 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | May 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
Abstract
The present invention provides an array substrate and a manufacturing method thereof. Etching stop patterns or auxiliary conductive patterns of a patterned auxiliary conductive layer are disposed corresponding to heavily doped regions of a patterned semiconductor layer, and source/drain electrodes may be electrically connected to the heavily doped regions via the etching stop patterns or the auxiliary conductive patterns. The production yield and the uniformity of electrical properties may be enhanced accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.