Dual conversion gain high dynamic range readout for comparator of double ramp analog to digital converter
US10615190B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2019 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Aug 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method includes coupling a low gain input of a dual stage comparator to establish a low conversion gain mode. An analog-to-digital (ADC) operation is performed to determine a low gain reset voltage. A low gain input is decoupled in response to a DCG control signal. A high gain input is coupled to establish a high conversion gain mode in response to the DCG control signal. The ADC operation is performed with the high gain input to determine a high gain reset voltage. The ADC operation is performed with the high gain input to determine a high gain signal voltage. The high gain input is decoupled in response to a DCG control signal transition. The low gain input is recoupled in response to the DCG control signal, and the ADC operation is performed with the low gain input to determine a low gain signal voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.