Array substrate with openings in insulation layer for auxiliary elecrode
US10615195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2017 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Nov 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2202/104
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed. Another photolithography and etching process is performed by using said photo mask to form first to third openings and a via hole in the second interlayered insulation layer, wherein along a normal direction, the third opening and the first contact hole are overlapped, the via hole and the second contact hole are overlapped, the first opening and the third contact hole are overlapped, and the second opening and the fourth contact hole are overlapped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.