Crest factor reduction
US10615778B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Feb 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.