Fully compensated complementary duty cycle correction circuits
US10615785B1 · kind B1 · utility
2Cited by
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20Claims
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Assignee
Inventors
Key dates
| Filing date | Mar 21, 2019 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Mar 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2472
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Duty cycle correction circuits are provided that include a serial combination of a first inverter and a second inverter for inverting an input clock signal into an output clock signal having a corrected duty cycle. The duty cycle correction circuits also include a serial combination of a third inverter and a fourth inverter for inverting a complement input clock signal into a complement output clock signal having a corrected duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.