Sub-sampling phase-locked loop
US10615807B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2019 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Jan 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY1 at a first point t1 in time and a second delay signal SDLY2 at a second point in time t2. The sampler module is configured to provide a first sample S1 of the oscillator output signal SOUT at the first point in time t1 and a second sample S2 of the oscillator output signal SOUT at the second point in time t2. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S1 and the second sample S2. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.