Flexible processor of a port extender device
US10616001B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | May 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a method for egress processing packets in a network device, a first stage engine, implemented in hardware, identifies a particular set of computer-readable instructions for a particular packet. The particular set of computer-readable instructions is identified from among a plurality of sets of computer-readable instructions stored in a memory, respective ones of the plurality of sets of computer-readable instructions being for performing different sets of egress processing operations with respect to different packets. A second stage processor, configured to execute computer-readable instructions stored in the memory, executes the particular set of computer-readable instructions, identified by the first stage engine, to perform the corresponding set of egress processing with respect to the particular packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.