Dynamic acceleration of data processor operations using data-flow analysis
US10620954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | May 18, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for dynamically determining when an operation, specified by one or more instructions in a data processing system, is suitable for accelerated execution. Data indicators are maintained, for data registers of the system, that indicate when data-flow from a register derives from a restricted source. In addition, instruction predicates are provided for instructions to indicate which instructions are capable of accelerated execution. From the data indicators and the instruction predicates, the microarchitecture of the data processing system determines, dynamically, when the operation is a thread-restricted function and suitable for accelerated execution in a hardware accelerator. The thread-restricted function may be executed on a hardware processor, such as a vector, neuromorphic or other processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.