System and methods for hardware-software cooperative pipeline error detection
US10621022B2 · kind B2 · utility
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6References
20Claims
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Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Jun 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.