Systems, methods, and apparatuses for stacked memory
US10621043B2 · kind B2 · utility
11Cited by
8References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Feb 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.