Systems and methods for transferring data with a dual-line first-in-first-out (FIFO) memory array
US10621122B1 · kind B1 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Jun 1, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.