Computing system for performing colorless routing for quadruple patterning lithography
US10621300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2017 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Jun 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.