Semiconductor package
US10622340B2 · kind B2 · utility
6Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2017 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Nov 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.