Display panel, manufacturing method thereof and display device
US10622422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Sep 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/80515
Abstract
Provided is a display panel, comprising: a substrate, and a planarization layer, an anode layer, a pixel definition layer, a cathode layer and an encapsulation layer sequentially stacked on the substrate; wherein in an edge area of the display panel, the pixel definition layer comprises a retaining wall group on the anode layer, comprising sub-retaining walls which are spaced apart, and the retaining wall group comprises a first side close to a display area and a second side away therefrom, wherein spaces of the sub-retaining walls form a path with a length greater than a straight line distance from the first side to the second side. The diffusion rate and diffusion range of the organic layer are controlled by performing anode hole optimization to form staggered sub-retaining walls, thereby reducing a number of edge retaining walls and reducing the edge area to increase a screen occupation ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.