Architecture and instruction set to support integer division
US10628126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Jun 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/535
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.