Patent · US Active

Core-only system management interrupt

US10628542B2 · kind B2 · utility

0Cited by

0References

22Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Tsvika Kurts · Haifa, IL
Alexander Gendler · Kiryat Motzkin, IL
Larisa Novakovsky · Haifa, IL
Anwar Azaarura Zaa'Rura · Nazareth, IL
Afik Sela · Ramat Gan, IL
Genadi Kazakevich · Haifa, IL
Alexandra Shainshein · Afula, IL
Ariel Sabba · Carmiel, IL

Key dates

Filing date	Jul 1, 2017
Grant date	Apr 21, 2020
Priority date	—
Expiry date	Mar 2, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2201/87
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.