Flow control in networking system-on-chip verification
US10628548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2017 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Mar 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for verifying networking system-on-chip designs comprises a reconfigurable hardware modeling device programmed to implement circuitry hardware models and a traffic generation device communicating with the reconfigurable hardware modeling device. The circuitry hardware models comprise a hardware model of a circuit design and a hardware model of interface circuitry. The system employs a backpressure flow control independent of the communication protocol, which can cause the traffic generation device to suspend sending messages when one or more message buffers in the traffic generation device, the reconfigurable hardware modeling device, or both cannot accept more messages based on predetermined conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.