Method and system for identifying defects of integrated circuits
US10628935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2017 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Mar 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for identifying defects in an integrated circuit are provided. The method includes receiving input data of a pattern associated with an integrated circuit, determining feature data associated with features of the pattern using the input data, determining defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determining a defect identification result using the defect detection results. The system includes a processor and a memory. The memory is coupled to the processor and configured to store a set of instructions to receive input data of a pattern associated with an integrated circuit, determine feature data associated with features of the pattern using the input data, determine defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determine a defect identification result using the defect detection results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.