Memory device including massbit counter and method of operating the same
US10629279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2018 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Jun 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.