Memory devices, memory systems and methods of operating memory devices
US10629286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2018 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Sep 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.