Memory and fabrication method thereof

US10629524B2 · kind B2 · utility

Assignees

• Semiconductor Manufacturing International (Shanghai) Corporation · CN
• Semiconductor Manufacturing International (Beijing) Corporation · CN

Inventors

• Peng Huang · Fuzhou, CN
• Xue-Hai Zhang · Kunshan, CN
• Chuan Zhou · Beijing, CN

Key dates

• Filing date: Feb 26, 2018
• Grant date: Apr 21, 2020
• Expiry date: Feb 26, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A memory and a method for fabricating the memory are provided. The memory includes a bit-line layer on a semiconductor substrate and having bit lines arranged in the bit-line layer. The memory also includes a shielding layer on the bit-line layer and having a conductive shielding structure arranged in the shielding layer. The conductive shielding structure is within a top-view projection area of the bit lines and is grounded. Further, the memory includes a word-line layer on the shielding layer and having word lines arranged in the word-line layer.